MEDIA ALERT: Andes Presents “Datacenter Accelerators Using RISC-V” at Linley Fall Processor Conference 2021

·2 min read

Santa Clara, Oct. 18, 2021 (GLOBE NEWSWIRE) --

What: The 2021 Linley Fall Processor Conference analyzes products and design strategies in a particular technology segment, providing information that engineers can immediately use to improve their designs. The event features in-depth technical presentations from Linley Group analysts as well as leading technologists from the industry. Andes Technology will present the first day of the conference and exhibit during the exhibition afterwa.

Who: Andes Technology Corp. John Min, Director of Applications, will present “Datacenter Accelerators Using RISC-V.” In his talk, he will show how Andes RISC-V NX27V processor IP leverages RISC-V’s strength to offer two most important features sought by accelerator SoC designers: powerful vector processing and efficient integration with hardware engine. He will also discuss the related system architecture and programming support.

Why: Andes Technology Corp.’s innovative configurable RISC-V platform solution is enabling designers to create unique, highly optimized system architectures and hardware/software partitioning, that shorten time-to-market and increase design quality.

Who should attend: SoC and ASIC chip architects, designers, and software developers.

When: The in-person component runs Wednesday and Thursday October 20 and 21. The virtual component of the conference runs Wednesday and Thursday October 27 and 28.

Where: The in-person event will be held at the Hyatt Regency Santa Clara located at 5101 Great America Pkwy, Santa Clara, CA 95054. To attend the virtual or in-person event, register at https://linleygroup.com/events/register.php?num=52

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation architecture AndeStar™ adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion. Andes is hiring. Engineers interested are encouraged to view the open positions on the Andes Technology LinkedIn page.

CONTACT: Jonah McLeod +1 (510) 449-8634 Jonahm@andestch.com


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